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ds056 (v2.0) april 3, 2007 www.xilinx.com 1 product specification ? 1998-2007 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as lis ted at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? 5 ns pin-to-pin logic delays ? system frequency up to 178 mhz ? 144 macrocells with 3,200 usable gates ? available in small footprint packages - 100-pin tqfp (81 user i/o pins) - 144-pin tqfp (117 user i/o pins) - 144-csp (117 user i/o pins) - pb-free available for all packages ? optimized for high-performance 3.3v systems - low power operation - 5v tolerant i/o pins accept 5v, 3.3v, and 2.5v signals - 3.3v or 2.5v output capability - advanced 0.35 micron feature size cmos fast flash? technology ? advanced system features - in-system programmable - superior pin-locking and routability with fast connect? ii switch matrix - extra wide 54-input function blocks - up to 90 product-terms per macrocell with individual product-term allocation - local clock inversion with three global and one product-term clocks - individual output enable per output pin with local inversion - input hysteresis on all user and boundary-scan pin inputs - bus-hold circuitry on all user pin inputs - full ieee standard 1149.1 boundary-scan (jtag) ? fast concurrent programming ? slew rate control on individual outputs ? enhanced data security features ? excellent quality and reliability - endurance exceeding 10,000 program/erase cycles - 20 year data retention - esd protection exceeding 2,000v ? pin-compatible with 5v-core xc95144 device in the 100-pin tqfp package warning: programming temperature range of t a = 0 c to +70 c description the xc95144xl is a 3.3v cpld targeted for high-perfor- mance, low-voltage applications in leading-edge communi- cations and computing systems. it is comprised of eight 54v18 function blocks, providing 3,200 usable gates with propagation delays of 5 ns. see figure 2 for overview. power estimation power dissipation in cplds can vary substantially depend- ing on the system frequency, design application and output loading. to help reduce power dissipation, each macrocell in a xc9500xl device may be configured for low-power mode (from the default high-performance mode). in addi- tion, unused product-terms and macrocells are automati- cally deactivated by the software to further conserve power. for a general estimate of i cc , the following equation may be used: i cc (ma) = mc hs (0.175*pt hs + 0.345) + mc lp (0.052*pt lp + 0.272) + 0.04 * mc tog (mc hs +mc lp )* f where: mc hs = # macrocells in high-speed configuration pt hs = average number of high-speed product terms per macrocell mc lp = # macrocells in low power configuration pt lp = average number of low power product terms per macrocell f = maximum clock frequency mctog = average % of flip-flops toggling per clock (~12%) this calculation was derived from laboratory measurements of an xc9500xl part filled with 16-bit counters and allowing a single output (the lsb) to be enabled. the actual i cc value varies with the design application and should be veri- fied during normal system operation. figure 1 shows the above estimation in a graphical form. for a more detailed discussion of power consumption in this device, see xilinx 0 xc95144xl high performance cpld ds056 (v2.0) april 3, 2007 00 product specification r
xc95144xl high performance cpld 2 www.xilinx.com ds056 (v2.0) april 3, 2007 product specification r application note xapp114, ?understanding xc9500xl cpld power.? figure 1: typical i cc vs. frequency for xc95144xl clock frequency (mhz) typical i cc (ma) 100 200 200 250 50 50 150 150 100 0 104 mhz hi gh performance 178 mhz low p owe r
xc95144xl high performance cpld ds056 (v2.0) april 3, 2007 www.xilinx.com 3 product specification r figure 2: xc95144xl architecture function block outputs (indicated by the bold line) drive the i/o blocks directly. in-system programming controller jtag controller i/o blocks function block 1 macrocells 1 to 18 macrocells 1 to 18 jtag port 3 54 i/o/gts i/o/gsr i/o/gck i/o i/o i/o i/o 4 1 i/o i/o i/o i/o 3 ds056_02_101300 1 function block 2 54 18 18 function block 3 macrocells 1 to 18 macrocells 1 to 18 54 function block 8 54 18 18 function block 4 macrocells 1 to 18 54 18 fast connect ii switch matrix
xc95144xl high performance cpld 4 www.xilinx.com ds056 (v2.0) april 3, 2007 product specification r absolute maximum ratings (2) recommended operation conditions quality and reliability characteristics dc characteristic over recommended operating conditions symbol description value units v cc supply voltage relative to gnd ?0.5 to 4.0 v v in input voltage relative to gnd (1) ?0.5 to 5.5 v v ts voltage applied to 3-state output (1) ?0.5 to 5.5 v t stg storage temperature (ambient) (3) ?65 to +150 o c t j junction temperature +150 o c notes: 1. maximum dc undershoot below gnd must be limited to either 0.5v or 10 ma, whichever is easier to achieve. during transitions, the device pins may undershoot to ?2.0 v or overshoot to +7.0v, provided this over- or undershoot lasts less than 10 ns and with th e forcing current being limited to 200 ma. external i/o voltage may not exceed v ccint by 4.0v. 2. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating condi tions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. 3. for soldering guidelines and thermal considerations, see the device packaging information on the xilinx website. for pb-free packages, see xapp427 . symbol parameter min max units v ccint supply voltage for internal logic and input buffers commercial t a = 0 o c to 70 o c3.0 3.6 v industrial t a = ?40 o c to +85 o c3.0 3.6 v v ccio supply voltage for output drivers for 3.3v operation 3.0 3.6 v supply voltage for output drivers for 2.5v operation 2.3 2.7 v v il low-level input voltage 0 0.80 v v ih high-level input voltage 2.0 5.5 v v o output voltage 0 v ccio v symbol parameter min max units t dr data retention 20 - years n pe program/erase cycles (endurance) 10,000 - cycles v esd electrostatic discharge (esd) 2,000 - volts symbol parameter test conditions min max units v oh output high voltage for 3.3v outputs i oh = ?4.0 ma 2.4 - v output high voltage for 2.5v outputs i oh = ?500 a90% v ccio -v v ol output low voltage for 3.3v outputs i ol = 8.0 ma - 0.4 v output low voltage for 2.5v outputs i ol = 500 a-0.4v i il input leakage current v cc = max; v in = gnd or v cc -10 a i ih i/o high-z leakage current v cc = max; v in = gnd or v cc -10 a
xc95144xl high performance cpld ds056 (v2.0) april 3, 2007 www.xilinx.com 5 product specification r ac characteristics i ih i/o high-z leakage current v cc = max; v ccio = max; v in = gnd or 3.6v -10 a v cc min < v in < 5.5v - 50 a c in i/o capacitance v in = gnd; f = 1.0 mhz - 10 pf i cc operating supply current (low power mode, active) v in = gnd, no load; f = 1.0 mhz 45 (typical) ma symbol parameter xc95144xl-5 xc95144xl-7 xc95144xl-10 units min max min max min max t pd i/o to output valid - 5.0 - 7.5 - 10.0 ns t su i/o setup time before gck 3.7 - 4.8 - 6.5 - ns t h i/o hold time after gck 0 - 0 - 0 - ns t co gck to output valid - 3.5 - 4.5 - 5.8 ns f system multiple fb internal operating frequency - 178.6 - 125.0 - 100.0 mhz t psu i/o setup time before p-term clock input 1.7 - 1.6 - 2.1 - ns t ph i/o hold time after p-term clock input 2.0 - 3.2 - 4.4 - ns t pco p-term clock output valid - 5.5 - 7.7 - 10.2 ns t oe gts to output valid - 4.0 - 5.0 - 7.0 ns t od gts to output disable - 4.0 - 5.0 - 7.0 ns t poe product term oe to output enabled - 7.0 - 9.5 - 11.0 ns t pod product term oe to output disabled - 7.0 - 9.5 - 11.0 ns t ao gsr to output valid - 10.0 - 12.0 - 14.5 ns t pao p-term s/r to output valid - 10.5 - 12.6 - 15.3 ns t wlh gck pulse width (high or low) 2.8 - 4.0 - 4.5 - ns t aprpw asynchronous preset/reset pulse width (high or low) 5.0 - 6.5 - 7.0 - ns t plh p-term clock pulse width (high or low) 5.0 - 6.5 - 7.0 - ns symbol parameter test conditions min max units figure 3: ac load circuit device output output type v test 3.3v 2.5v v test r 1 320 250 r 1 r 2 c l r 2 360 660 c l 35 pf 35 pf ds058_03_081500 v ccio 3.3v 2.5v
xc95144xl high performance cpld 6 www.xilinx.com ds056 (v2.0) april 3, 2007 product specification r internal timing parameters symbol parameter xc95144xl-5 xc95144xl-7 xc95144xl-10 units min max min max min max buffer delays t in input buffer delay - 1.5 - 2.3 - 3.5 ns t gck gck buffer delay - 1.1 - 1.5 - 1.8 ns t gsr gsr buffer delay - 2.0 - 3.1 - 4.5 ns t gts gts buffer delay - 4.0 - 5.0 - 7.0 ns t out output buffer delay - 2.0 - 2.5 - 3.0 ns t en output buffer enable/disable delay -0-0-0ns product term control delays t ptck product term clock delay - 1.6 - 2.4 - 2.7 ns t ptsr product term set/reset delay - 1.0 - 1.4 - 1.8 ns t ptts product term 3-state delay - 5.5 - 7.2 - 7.5 ns internal register and combinatorial delays t pdi combinatorial logic propagation delay - 0.5 - 1.3 - 1.7 ns t sui register setup time 2.3 - 2.6 - 3.0 - ns t hi register hold time 1.4 - 2.2 - 3.5 - ns t ecsu register clock enable setup time 2.3 - 2.6 - 3.0 - ns t echo register clock enable hold time 1.4 - 2.2 - 3.5 - ns t coi register clock to output valid time - 0.4 - 0.5 - 1.0 ns t aoi register async. s/r to output delay - 6.0 - 6.4 - 7.0 ns t rai register async. s/r recover before clock 5.0 7.5 10.0 ns t logi internal logic delay - 1.0 - 1.4 - 1.8 ns t logilp internal low power logic delay - 5.0 - 6.4 - 7.3 ns feedback delays t f fast connect ii feedback delay - 1.9 - 3.5 - 4.2 ns time adders t pta incremental product term allocator delay - 0.7 - 0.8 - 1.0 ns t slew slew-rate limited delay - 3.0 - 4.0 - 4.5 ns
xc95144xl high performance cpld ds056 (v2.0) april 3, 2007 www.xilinx.com 7 product specification r xc95144xl i/o pins (2) function block macro- cell tq100 tq144 cs144 bscan order function block macro- cell tq100 tq144 cs144 bscan order 11-23h342931-39m3321 121116f142632 (1) 23 (1) 32 (1) l1 (1) 318 1 3 12 17 g2 423 3 3 - 41 k4 315 14-25j142034-44n4312 1 5 13 19 g3 417 3 5 24 33 l2 309 1 6 14 20 g4 414 3 6 25 34 l3 306 17---411 37-46l5303 1 8 15 21 h1 408 3 8 (1) 27 (1) 38 (1) n2 (1) 300 1 9 16 22 h2 405 3 9 28 40 n3 297 1 10 - 31 k3 402 3 10 - 48 n5 294 1111724h4399 3112943m4291 1121826j2396 3123045k5288 1 13 - - - 393 3 13 - - - 285 1141927j3390 3143249k6282 1152028j4387 3153350l6279 1 16 - 35 m1 384 3 16 - - - 276 117 (1) 22 (1) 30 (1) k2 (1) 381 3 17 34 51 m6 273 1 18 - - - 378 3 18 - - - 270 2 1 - 142 c3 375 4 1 - 118 c9 267 22 (1) 99 (1) 143 (1) a2 (1) 372 4 2 87 126 a7 264 23---36943-133a5261 2 4 - 4 c1 366 4 4 - - - 258 25 (1) 1 (1) 2 (1) b1 (1) 363 4 5 89 128 d7 255 26 (1) 2 (1) 3 (1) c2 (1) 360 4 6 90 129 a6 252 27---35747---249 28 (1) 3 (1) 5 (1) d4 (1) 354 4 8 91 130 b6 246 29 (1) 4 (1) 6 (1) d3 (1) 351 4 9 92 131 c6 243 2 10 - 7 d2 348 4 10 - 135 c5 240 21169e4345 41193132d6237 2 12 7 10 e3 342 4 12 94 134 b5 234 2 13 - 12 e1 339 4 13 - 137 a4 231 2 14 8 11 e2 336 4 14 95 136 d5 228 2 15 9 13 f4 333 4 15 96 138 b4 225 2 16 - 14 f3 330 4 16 - 139 c4 222 2 17 1015f2327 4 17 97140a3219 2 18 - - - 324 4 18 - - - 216 notes: 1. global control pin. 2. the pin-outs are the same for pb-free versions of packages.
xc95144xl high performance cpld 8 www.xilinx.com ds056 (v2.0) april 3, 2007 product specification r xc95144xl (continued) function block macro- cell tq100 tq144 cs144 bscan order function block macro- cell tq100 tq144 cs144 bscan order 5 1 ---213 7 1 ---105 5 2 35 52 n6 210 7 2 50 71 n12 102 53-59l8207 73-75l1299 5 4 ---204 7 4 ---96 5 5 36 53 m7 201 7 5 52 74 m13 93 5 6 37 54 n7 198 7 6 53 76 l13 90 5 7 - 66 m10 195 7 7 - 77 k10 87 5 8 39 56 k7 192 7 8 54 78 k11 84 5 9 40 57 n8 189 7 9 55 80 k13 81 5 10 ?- 68 n11 186 7 10 - 79 k12 78 5114158m8183 7115682j1175 5 124260k8180 7 125885h1072 5 13 - 70 l11 177 7 13 - 81 j10 69 5 144361n9174 7 145986h1166 5 154664k9171 7 156087h1263 5 16 - - - 168 7 16 - 83 j12 60 5 17 49 69 m11 165 7 17 61 88 h13 57 5 18 ---162 7 18 ---54 6 1 ---159 8 1 ---51 6 2 74 106 c11 156 8 2 63 91 g11 48 6 3 ---153 8 3 -95f1145 64-111b11150 84-97e1342 6 5 76 110 a12 147 8 5 64 92 g10 39 6 6 77 112 a11 144 8 6 65 93 f13 36 6 7 ---141 8 7 ---33 6 8 78 113 d10 138 8 8 66 94 f12 30 6 9 79 116 a10 135 8 9 67 96 f10 27 6 10 - 115 b10 132 8 10 - 101 d13 24 6 11 80 119 b9 129 8 11 68 98 e12 21 6 12 81 120 a9 126 8 12 70 100 e10 18 6 13 - - - 123 8 13 - 103 d11 15 6 14 82 121 d8 120 8 14 71 102 d12 12 6 15 85 124 a8 117 8 15 72 104 c13 9 6 16-117d9114 8 16-107b136 6 1786125b7111 8 1773105c123 6 18 ---108 8 18 ---0 notes: 1. the pin-outs are the same for pb-free versions of packages.
xc95144xl high performance cpld ds056 (v2.0) april 3, 2007 www.xilinx.com 9 product specification r xc95144xl global, jtag and power pins (1) pin type tq100 tq144 cs144 i/o/gck1 22 30 k2 i/o/gck2 23 32 l1 i/o/gck3 27 38 n2 i/o/gts1 3 5 d4 i/o/gts2 4 6 d3 i/o/gts3 1 2 b1 i/o/gts4 2 3 c2 i/o/gsr 99 143 a2 tck 48 67 l10 tdi4563l9 tdo 83 122 c8 tms 47 65 n10 v ccint 3.3v 5, 57, 98 8, 42, 84, 141 b3, d1, j13, l4 v ccio 2.5v/3.3v 26, 38, 51, 88 1, 37, 55, 73, 109, 127 a1, a13, c7, l7, n1, n13 gnd 21, 31, 44, 62, 69, 75, 84, 100 18, 29, 36, 47, 62, 72, 89, 90, 99, 108, 114, 123, 144 b2, b8, b12, c10, e11, g1, g12, g13, k1, m2, m5, m9, m12 no connects - ? ? notes: 1. the pin-outs are the same for pb-free versions of packages.
xc95144xl high performance cpld 10 www.xilinx.com ds056 (v2.0) april 3, 2007 product specification r device part marking and ordering combination information. device ordering and part marking number speed (pin-to-pin delay) pkg. symbol no. of pins package type operating range (1) xc95144xl-5tq100c 5 ns tq100 100-pin thin quad flat pack (tqfp) c xc95144xl-5tq144c 5 ns tq144 144-pin thin quad flat pack (tqfp) c xc95144xl-5cs144c 5 ns cs144 144-ball chip scale package (csp) c xc95144xl-7tq100c 7.5 ns tq100 100-pin thin quad flat pack (tqfp) c xc95144xl-7tq144c 7.5 ns tq144 144-pin thin quad flat pack (tqfp) c xc95144xl-7cs144c 7.5 ns cs144 144-ball chip scale package (csp) c xc95144xl-7tq100i 7.5 ns tq100 100-pin thin quad flat pack (tqfp) i xc95144xl-7tq144i 7.5 ns tq144 144-pin thin quad flat pack (tqfp) i xc95144xl-7cs144i 7.5 ns cs144 144-ball chip scale package (csp) i xc95144xl-10tq100c 10 ns tq100 100-pin thin quad flat pack (tqfp) c xc95144xl-10tq144c 10 ns tq144 144-pin thin quad flat pack (tqfp) c xc95144xl-10cs144c 10 ns cs144 144-ball chip scale package (csp) c xc95144xl-10tq100i 10 ns tq100 100-pin thin quad flat pack (tqfp) i xc95144xl-10tq144i 10 ns tq144 144-pin thin quad flat pack (tqfp) i xc95144xl-10cs144i 10 ns cs144 144-ball chip scale package (csp) i xc95144xl-5tqg100c 5 ns tqg100 100-pin thin quad flat pack (tqfp); pb-free c xc95144xl-5tqg144c 5 ns tqg144 144-pin thin quad flat pack (tqfp); pb-free c xc95144xl-5csg144c 5 ns csg144 144-ball chip scale package (csp); pb-free c xc95144xl-7tqg100c 7.5 ns tqg100 100-pin thin quad flat pack (tqfp); pb-free c xc95144xl-7tqg144c 7.5 ns tqg144 144-pin thin quad flat pack (tqfp); pb-free c xc95144xl-7csg144c 7.5 ns csg144 144-ball chip scale package (csp); pb-free c xc95144xl-7tqg100i 7.5 ns tqg100 100-pin thin quad flat pack (tqfp); pb-free i xc95144xl-7tqg144i 7.5 ns tqg144 144-pin thin quad flat pack (tqfp); pb-free i xc95144xl-7csg144i 7.5 ns csg144 144-ball chip scale package (csp); pb-free i xc95xxxxl tq144 7c device type package speed operating range this line not related to device part number sample package with part marking. r 1
xc95144xl high performance cpld ds056 (v2.0) april 3, 2007 www.xilinx.com 11 product specification r warranty disclaimer these products are subject to the terms of the xilinx limited warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of the products in an application or environment that is not within the specifications stated on the then-current xilinx data sheet for the produc ts. products are not designed to be fail-safe and are not warranted for use in applications th at pose a risk of physical harm or loss of life. use of products in such applications is fully at the risk of customer subject to applicable laws and regulations. further reading the following xilinx links go to relevant xc9500xl cpld documentation, including xapp111, using the xc9500xl timing model, and xapp784, bulletproof cpld design practices. simply click on the link and scroll down. data sheets, application notes, and white papers. packaging XC95144XL-10TQG100C 10 ns tqg100 100-pin thin quad flat pack (tqfp); pb-free c xc95144xl-10tqg144c 10 ns tqg144 144-pin thin quad flat pack (tqfp); pb-free c xc95144xl-10csg144c 10 ns csg144 144-ball chip scale package (csp); pb-free c xc95144xl-10tqg100i 10 ns tqg100 100-pin thin quad flat pack (tqfp); pb-free i xc95144xl-10tqg144i 10 ns tqg144 144-pin thin quad flat pack (tqfp); pb-free i xc95144xl-10csg144i 10 ns csg144 144-ball chip scale package (csp); pb-free i notes: 1. c = commercial: t a = 0 to +70c; i = industrial: t a = ?40 to +85c device ordering and part marking number speed (pin-to-pin delay) pkg. symbol no. of pins package type operating range (1) standard example: xc95144xl device speed grade package type number of pins temperature range -4 tq c 144 pb- free example: xc95144xl tq g 144 c device speed grade package type pb -free number of pins -4 temperature range
xc95144xl high performance cpld 12 www.xilinx.com ds056 (v2.0) april 3, 2007 product specification r revision history the following table shows the revision history for this document. date version revision 10/30/98 1.1 minor corrections to cs144 pinout table. 11/13/98 1.2 v1.2 minor correction in cs144 pinout table. 06/20/02 1.3 updated i cc equation, page 1. updated dc characteristics: i cc to 45 (typical). updated component availability chart.added additional i ih test conditions and measurements to dc characteristics table. 06/20/03 1.4 updated t sol from 260 to 220 o c. added part marking and updated ordering information. 08/21/03 1.5 updated package device marking pin 1 orientation. 07/15/04 1.6 added pb-free documentation 09/15/04 1.7 added t aprpw specification to ac characteristics. 07/15/05 1.8 move to product specification 03/22/06 1.9 add warranty disclaimer. 04/03/07 2.0 add programming temperature range warning on page 1.

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